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3.3 V, 3.2 Gbps, Limiting Amplifier ADN2891
FEATURES
Input sensitivity: 4 mV p-p 80 ps rise/fall times CML outputs: 700 mV p-p differential Programmable LOS detector: 3.5 mV to 35 mV Rx signal strength indicator (RSSI) SFF-8472-compliant average power measurement Single-supply operation: 3.3 V Low power dissipation: 145 mW Available in space-saving 3 mm x 3 mm, 16-lead LFCSP Extended temperature range: -40C to +95C SFP reference design available
GENERAL DESCRIPTION
The ADN2891 is a 3.2 Gbps limiting amplifier with integrated loss-of-signal (LOS) detection circuitry and a received signal strength indicator (RSSI). This part is optimized for SONET, Gigabit Ethernet (GbE), and Fibre Channel optoelectronic conversion applications. The ADN2891 has a differential input sensitivity of 4 mV p-p and accepts up to a 2.0 V p-p differential input overload voltage. The ADN2891 supports current mode logic (CML) outputs with controlled rise and fall times. By monitoring the bias current through a photodiode, the onchip RSSI detector measures the average power received with 2% typical linearity over the entire valid input range of the photodiode. The on-chip RSSI detector facilitates SFF-8472compliant optical transceivers by eliminating the need for external RSSI detector circuitry. Additional features include a programmable loss-of-signal (LOS) detector and output squelch. The ADN2891 is available in a 3 mm x 3 mm, 16-lead LFCSP.
APPLICATIONS
SFP/SFF/GBIC optical transceivers OC-3/OC-12/OC-48, GbE, Fibre Channel (FC) receivers 10GBASE-LX4 transceivers WDM transponders
FUNCTIONAL BLOCK DIAGRAM
AVCC AVEE DRVCC DRVCC DRVEE
ADN2891
50 PIN 50 OUTP OUTN 50 50 3k PD_VCC PD_CATHODE
05244-001
ADN2880
NIN
+V VREF LOS RSSI/LOS DETECTOR 10k
RSSI_OUT
ADuC7020
CAZ1 0.01F
CAZ2
THRADJ SQUELCH
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2005 Analog Devices, Inc. All rights reserved.
ADN2891 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 10 Limiting Amplifier ..................................................................... 10 Loss of Signal (LOS) Detector .................................................. 10 Received Signal Strength Indicator (RSSI) ............................. 10 Squelch Mode ............................................................................. 10 Applications..................................................................................... 11 PCB Design Guidelines ............................................................. 11 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 13
REVISION HISTORY
7/05--Rev. 0 to Rev. A Changes to Table 1............................................................................ 3 Changes to Ordering Guide .......................................................... 13 3/05--Revision 0: Initial Version
Rev. A | Page 2 of 16
ADN2891 SPECIFICATIONS
Test Conditions: VCC = 2.9 V to 3.6 V, VEE = 0 V, TA = -40C to +95C, unless otherwise noted. Table 1.
Parameter QUANTIZER DC CHARACTERISTICS Input Voltage Range Input Common Mode Differential Input Range Differential Input Sensitivity Input Offset Voltage Input RMS Noise Input Resistance Input Capacitance QUANTIZER AC CHARACTERISTICS Input Data Rate Small Signal Gain S11 S22 Random Jitter Deterministic Jitter Low Frequency Cutoff Power Supply Rejection Ratio LOSS OF SIGNAL DETECTOR (LOS) LOS Assert Level Electrical Hysteresis LOS Assert Time LOS De-Assert Time RSSI Input Current Range RSSI Output Linearity Gain Offset Compliance Voltage POWER SUPPLIES VCC ICC OPERATING TEMPERATURE RANGE CML OUTPUT CHARACTERISTICS Output Impedance Output Voltage Swing Output Rise and Fall Time Min 1.8 2.1 5.2 3.5 100 235 50 0.65 3200 50 -10 -10 4.0 9.0 30 1.0 45 Typ Max 2.8 2.7 2.0 Unit V p-p V V p-p mV p-p V V rms pF Mb/s dB dB dB ps rms ps p-p kHz kHz dB Test Conditions/Comments At PIN or NIN, dc-coupled DC-coupled AC-coupled 3.2 Gbps, PRBS 223 - 1, BER 10-10
Single-ended
155
6.4 34
Differential Differential, f < 3.2 GHz Differential, f < 3.2 GHz Input 10 mV p-p, OC-48, PRBS 223 - 1 Input 10 mV p-p, OC-48, PRBS 223 - 1 CAZ = Open CAZ = 0.0 1 F f < 10 MHz
1.9 19 2.4 2.75
3.5 35 5.0 5.0 950 62
5.6 53
mV p-p mV p-p dB dB ns ns A % mA/mA nA V
RTHRADJ = 100 k RTHRADJ = 1 k OC-3, PRBS 223 - 1 OC-48, PRBS 223 - 1 DC-coupled DC-coupled
5 2 1.0 145 VCC - 0.9
1000
VCC - 0.4
5 A < IIN 1000 A IRSSI/IPD Difference between measured RSSI output and PD_CATHODE (input) current of 5 A Measured at PD_CATHODE, with I = 5 A or I = 1 mA
2.9 -40
3.3 45 +25 50 660 80
3.6 49 +95
V mA C mV p-p ps
TMIN to TMAX Single-ended Differential 20% to 80%
600
850 130
Rev. A | Page 3 of 16
ADN2891
Parameter LOGIC INPUTS (SQUELCH) VIH, Input High Voltage VIL, Input Low Voltage Input Current LOGIC OUTPUTS (LOS) VOH, Output High Voltage VOL, Output Low Voltage Min 2.0 0.8 40 6 2.4 0.4 Typ Max Unit V V A A V V Test Conditions/Comments
IINH, VIN = 2.4 V, 100 k pull-down resistor on-chip IINL, VIN = 0.4 V, 100 k pull-down resistor on-chip Open drain output, 4.7 k to 10 k pull-up resistor to VCC Open drain output, 4.7 k to 10 k pull-up resistor to VCC
Rev. A | Page 4 of 16
ADN2891 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Power Supply Voltage Minimum Voltage (All Inputs and Outputs) Maximum Voltage (All Inputs and Outputs) Storage Temperature Operating Temperature Range Production Soldering Temperature Junction Temperature Rating 4.2 V VEE - 0.4 V VCC + 0.4 V -65C to +150C -40C to +95C J-STD-20 125C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for 4-layer PCB with exposed paddle soldered to GND. Table 3.
Package Type 3 mm x 3 mm, 16-lead LFCSP JA 28 Unit C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 5 of 16
ADN2891 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PD_CATHODE RSSI_OUT
14 7
16
15
AVCC 1 PIN 2
13 12 DRVCC
11 OUTP TOP VIEW NIN 3 (Not to Scale) 10 OUTN AVEE 4 9 DRVEE 5 6 8
ADN2891
CAZ1
THRADJ
CAZ2
LOS
SQUELCH
PD_VCC
Figure 2. Pin Configuration
Note that the LFCSP has an exposed pad on the bottom. To improve heat dissipation, the exposed pad must be soldered to the GND plane with filled vias. Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Exposed Pad
1
Mnemonic AVCC PIN NIN AVEE THRADJ CAZ1 CAZ2 LOS DRVEE OUTN OUTP DRVCC SQUELCH RSSI_OUT PD_VCC PD_CATHODE Pad
I/O Type 1 P AI AI P AO AI AI DO P DO DO P DI AO P AO P
Descriptions Analog Power Supply. Differential Data Input, Positive Port, 50 On-Chip Termination. Differential Data Input, Negative Port, 50 On-Chip Termination. Analog Ground. LOS Threshold Adjust Resistor. If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for input offset correction. If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for input offset correction. LOS Detector Output, Open Collector. Output Buffer Ground. Differential Data Output, CML, Negative Port, 50 On-Chip Termination. Differential Data Output, CML, Positive Port, 50 On-Chip Termination. Output Buffer Power Supply. Disable Outputs, 100 k On-Chip Pull-Down Resistor. Average Current Output. Power Input for RSSI Measurement. Photodiode Bias Voltage. Connect to Ground.
P = power; DI = digital input; DO = digital output; AI = analog input; and AO = analog output.
Rev. A | Page 6 of 16
05244-002
ADN2891 TYPICAL PERFORMANCE CHARACTERISTICS
100mV/DIV
100mV/DIV
50ps/DIV
50ps/DIV
Figure 3. Eye of ADN2891 @ 25C, 3.2 Gbps, and 10 mV Input
Figure 6. Eye of ADN2891 @ 95C, 3.2 Gbps, and 500 mV Input
100mV/DIV
100mV/DIV
50ps/DIV
1ns/DIV
Figure 4. Eye of ADN2891 @ 25C, 3.2 Gbps, and 500 mV Input
Figure 7. Eye of ADN2891 @ 25C, 155 Mbps, and 10 mV Input
100mV/DIV
50ps/DIV
Figure 5. Eye of ADN2891 @ 95C, 3.2 Gbps, and 10 mV Input
Rev. A | Page 7 of 16
05244-027
05244-017
05244-019
05244-020
05244-015
ADN2891
70 60
LOS TRIP AND RELEASE (mV)
5.0 4.5
-40C
RANDOM JITTER (ps)
05244-011
4.0
50 40 +95C 30
+95C +25C
3.5 3.0 2.5 2.0 1.5 1.0
+25C 20 DEASSERTION -40C
ASSERTION 0 1k 10k RTH ()
0.5 0 0 0.5 1.0 1.5 2.0 DATA RATE (Gbps) 2.5 3.0 3.5
100k
Figure 8. LOS Trip and Release vs. RTH at OC48
8 OC48 6
Figure 11. Random Jitter vs. Data Rate
14
LOS ELECTRICAL HYSTERESIS (dB)
12
DETERMINISTIC JITTER (ps)
10
OC3 4
8
6
2
05244-012
4
0 1k
10k RTH ()
100k
0 0 0.5 1.0 1.5 2.0 DATA RATE (Gbps) 2.5 3.0 3.5
Figure 9. LOS Electrical Hysteresis vs. RTH at 25C
18 16 14 12
SAMPLE
POWER SUPPLY-NOISE REJECTION (dB)
Figure 12. Deterministic Jitter vs. Data Rate
70
60
50
10 8 6 4 2 0 6.0 6.3 6.6 6.9 7.2 7.5 7.8 8.1 8.4 ELECTRICAL HYSTERESIS (dB) 8.7 9.0
05244-022
40
30 20
0 100k
1M SUPPLY-NOISE FREQUENCY (Hz)
10M
Figure 10. Sample Lot Distribution--Worst-Case Condition: Conditions = 155 Mbps, 100 k @ 95C, 3.6 V
Rev. A | Page 8 of 16
Figure 13. PSRR vs. Supply-Noise Frequency
05244-005
10
05244-013
2
05244-010
10
ADN2891
1200
900 800
1000
RSSI OUTPUT CURRENT (A)
5A REFERRED OFFSET (nA)
05244-018
700 600 500 400 300 200 100 0 -40
05244-025
800
600
400
200
0 0
200 400 600 800 1000 1200 PD_CATHODE CURRENT (PHOTODIODE CURRENT) (A)
-20
0
20 40 TEMPERATURE (C)
60
80
100
Figure 14. RSSI Output vs. Average Photodiode Current
60
Figure 17. RSSI Offset is the Difference Between Measured RSSI Output and PD_CATHODE (Input) Current of 5 A
5.0 4.5
50
RSSI OUTPUT CURRENT (A)
RSSI LINEARITY (%)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 +100C +30C
40
30
20
10
05244-028
0.5 0 0 200 400 600 PD_CATHODE CURRENT (A) 800
-40C
0 0 10 20 30 40 50 60 PD_CATHODE CURRENT (PHOTODIODE CURRENT) (A)
1000
Figure 15. RSSI Output vs. Average Photodiode Current (Zoomed)
-0.15 -0.20
44.0 44.5
Figure 18. RSSI Linearity % vs. PD_CATHODE Current
COMPLIANCE VOLTAGE REFERRED TO VCC (V)
-0.25 -0.30 -0.35 -0.40 -0.45 -0.50 -0.55 -0.60 -0.65 -0.70 0 100 200 300 400 500 600 700 INPUT CURRENT (A) 800 900
05244-023
43.5
ICC (mA)
43.0
42.5
42.0
1000
41.0 -60
-40
-20
0 20 40 60 TEMPERATURE (C)
80
100
120
Figure 16. PD_CATHODE Compliance Voltage vs. Input Current RSSI (Refer to VCC)
Figure 19. ADN2891 ICC Current vs. Temperature
Rev. A | Page 9 of 16
05244-024
41.5
05244-029
ADN2891 THEORY OF OPERATION
LIMITING AMPLIFIER
Input Buffer
The ADN2891 limiting amplifier provides differential inputs (PIN/NIN), each having single-ended, on-chip, 50 termination. The amplifier can accept either dc-coupled or ac-coupled signals; however, an ac-coupled signal is recommended. Using a dc-coupled signal, the amplifier needs a correct input commonmode voltage and enough headroom to handle the dynamic input signal strength. Additionally, TIA output offset drifts may degrade receiver performance. The ADN2891 limiting amplifier is a high gain device. It is susceptible to dc offsets in the signal path. The pulse width distortion presented in the NRZ data or a distortion generated by the TIA may appear as dc offset or a corrupted signal to the ADN2891 inputs. An internal offset correction loop can compensate for certain levels of offset. To compensate for more offset, an external capacitor connected between the CAZ1 and CAZ2 pins maybe necessary. For GbE and FC applications, no external capacitor is necessary; however, for SONET applications, a 0.01 F capacitor helps the input signal offset compensation and provides a 3 dB cutoff frequency at 1 kHz.
LOSS OF SIGNAL (LOS) DETECTOR
The on-chip LOS circuit drives LOS to logic high when the input signal level falls below a user-programmable threshold. The threshold level can be set to anywhere from 3.5 mV p-p to 35 mV p-p, typical, and is set by a resistor connected between the THRADJ pin and VEE. See Figure 8 and Figure 9 for the LOS threshold vs. THRADJ. The ADN2891 LOS circuit has an electrical hysteresis greater than 2.5 dB to prevent chatter at the LOS signal. The LOS output is an open-collector output that must be pulled up externally with a 4.7 k to 10 k resistor.
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)
The ADN2891 has an on-chip, RSSI circuit. By monitoring the current supplied to the photodiode, the RSSI circuit provides an accurate, average power measurement. The output of the RSSI is a current that is directly proportional to the average amount of PIN photodiode current. Placing a resistor between the RSSI_OUT pin and GND converts the current to a GND referenced voltage. This function eliminates the need for external RSSI circuitry for SFF-8472-compliant optical receivers. For more information, see Figure 14 to Figure 18.
SQUELCH MODE
Driving the SQUELCH input to logic high disables the limiting amplifier outputs. Using LOS output to drive the SQUELCH input, the limiting amplifier outputs stop toggling anytime a signal input level to the limiting amplifier drops below the programmed LOS threshold. The SQUELCH pin has a 100 k, internal, pull-down resistor.
CML Output Buffer
The ADN2891 provides differential CML outputs, OUTP and OUTN. Each output has an internal 50 termination to VCC.
Rev. A | Page 10 of 16
ADN2891 APPLICATIONS
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used to ensure optimal performance. The exposed pad should connect to the GND plane using filled vias so that solder does not leak through the vias during reflow. Using filled vias in parallel under the package greatly reduces the thermal resistance and enhances the reliability of the connectivity of the exposed pad to the GND plane during reflow. To reduce power noise, a 10 F electrolytic decoupling capacitor between power and ground should be close to where the 3.3 V supply enters the PCB. The other 0.1 F and 1 nF ceramic chip decoupling capacitors should be close to the VCC and VEE pins to provide better decouple filtering and a shorter current return loop.
Output Buffer Power Supply and Ground Planes
Pin 9 (DRVEE) and Pin 12 (DRVCC) are the power supply and ground pins that provide current to the differential output buffer. To reduce possible series inductance, Pin 9, which is the ground return of the output buffer, should connect to ground directly. If the ground plane is an internal plane and connections to the ground plane are vias, multiple vias in parallel to ground can reduce series inductance. Similarly, to reduce the possible series inductance, Pin 12, which supplies power to the high speed differential OUTP/OUTN output buffer, should connect to the power plane directly. If the power plane is an internal plane and connections to the power plane are vias, multiple vias in parallel can reduce the series inductance, especially on Pin 12. See Figure 20 for the recommended connections.
VCC C9
PD_CATHODE
VCC 0.1F VCC C5 C6 AVCC C1 PIN NIN AVEE
1 2 3 4
RSSI_OUT
SQUELCH
PD_VCC
R1
C10
RSSI MEASUREMENT TO ADC
VCC C7
12 11 10 9
16
15
14
13
C8
ADN2891
CONNECT EXPOSED PAD TO GND
DRVCC OUTP C3 OUTN C4 DRVEE TO HOST BOARD
ADN2880
C2
5
6
7
8
CAZ1
THRADJ
CAZ2
LOS
C1-C4, C11: 0.01F X5R/X7R DIELECTRIC, 0201 CASE C5, C7, C9, C10, C12: 0.1F X5R/X7R DIELECTRIC, 0402 CASE C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE R3 4.7k TO 10k ON HOST BOARD
C11 C12 R2
VCC
Figure 20. Typical Applications Circuit (Example of Using PIN PD and On-Chip RSSI Detector)
Rev. A | Page 11 of 16
05244-008
ADN2891
PCB Layout
Figure 21 shows the recommended PCB layout. The 50 transmission lines are the traces that bring the high frequency input and output signals (PIN, NIN, OUTP, and OUTN) to the SMA connectors with minimum reflection. To avoid a signal skew between the differential traces, each differential PIN/NIN and OUTP/OUTN pair should have matched trace lengths from the signal pins to the corresponding SMA connectors. C1, C2, C3, and C4 are ac coupling capacitors in series with the high speed, signal input/output paths. To minimize the possible mismatch, the ac coupling capacitor pads should be the same width as the 50 transmission line trace width. To reduce supply noise, a 1 nF decoupling capacitor should be placed on the same layer as close as possible to the VCC pins. A 0.1 F decoupling capacitor can be placed on the bottom of the PCB directly underneath the 1 nF capacitor. All high speed, CML outputs have internal 50 resistor termination between the output pin and VCC. The high speed inputs, PIN and NIN, also have the internal 50 termination to an internal reference voltage. As with any high speed, mixed-signal design, keep all high speed digital traces away from sensitive analog nodes.
Soldering Guidelines for the LFCSP
The lands on the 16-lead LFCSP are rectangular. The PCB pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the LFCSP has a central exposed pad. The pad on the printed circuit board should be at least as large as the exposed pad. Users must connect the exposed pad to VEE using filled vias so that solder does not leak through the vias during reflow. This ensures a solid connection from the exposed pad to VEE.
R1, C9, C10 ON BOTTOM TO ROSA DOUBLE-VIAS TO REDUCE INDUCTANCE TO SUPPLY AND GND PLACE C7 ON BOTTOM OF BOARD UNDERNEATH C8 C8 VIAS TO GND NIN C2 C4 OUTN C3 OUTP
PLACE C5 ON BOTTOM OF BOARD UNDERNEATH C6 C1 PIN C6
1
EXPOSED PAD
4mm
DOUBLE-VIA TO GND TO REDUCE INDUCTANCE
05244-009
VIA TO C12, R2 ON BOTTOM C11 VIA TO BOTTOM
Figure 21. Recommended PCB Layout (Top View)
Rev. A | Page 12 of 16
ADN2891 OUTLINE DIMENSIONS
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 0.90 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 1.50 REF 0.60 MAX 0.50 0.40 0.30
PIN 1 INDICATOR
13 12
16
1
*1.65 1.50 SQ 1.35
EXPOSED PAD
9 (BOTTOM VIEW) 4 8 5
0.25 MIN
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 22. 16-Lead Lead Frame Chip Scale Package [VQ_LFCSP] 3 mm x 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADN2891ACPZ-500RL7 1 ADN2891ACPZ-RL71 ADN2891ACPZ-RL1 EVAL-ADN2891EB
1
Temperature Range -40C to +95C -40C to +95C -40C to +95C
Package Description 16-Lead VQ_LFCSP, 500 pieces 16-Lead VQ_LFCSP, 1,500 pieces 16-Lead VQ_LFCSP, 5,000 pieces Evaluation Board
Package Option CP-16-3 CP-16-3 CP-16-3
Branding F04 F04 F04
Z = Pb-free part.
Rev. A | Page 13 of 16
ADN2891 NOTES
Rev. A | Page 14 of 16
ADN2891 NOTES
Rev. A | Page 15 of 16
ADN2891 NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05244-0-7/05(A)
Rev. A | Page 16 of 16

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